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Micron NAND Flash devices include an asynchronous data interface for high-performance I/O operations. These devices use a highly multiplexed 8-bit bus (DQx) to transfer commands, address, and data. There are five control signals used to implement the asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control hardware write protection (WP#) and monitor device status (R/B#). This Micron NAND Flash device additionally includes a synchronous data interface for high-performance I/O operations. When the synchronous interface is active, WE# becomes CLK and RE# becomes W/R#. Data transfers include a bidirectional data strobe (DQS). This hardware interface creates a low pin-count device with a standard pinout that remains the same from one density to another, enabling future upgrades to higher densities with no board redesign. A target is the unit of memory accessed by a chip enable signal. A target contains one or more NAND Flash die. A NAND Flash die is the minimum unit that can independently execute commands and report status. A NAND Flash die, in the ONFI specification, is referred to as a logical unit (LUN). For further details, see Device and Array Organization.

• Open NAND Flash Interface (ONFI) 2.2-compliant1
• Multiple-level cell (MLC) technology
• Organization
  • Page size x8: 8640 bytes (8192 + 448 bytes)
  • Block size: 256 pages (2048K + 112K bytes)
  • Plane size: 2 planes x 2048 blocks per plane
  • Device size: 64Gb: 4096 blocks;
  • 128Gb: 8192 blocks;
  • 256Gb: 16,384 blocks;
  • 512Gb: 32,786 blocks
• Synchronous I/O performance
  • Up to synchronous timing mode 5
  • Clock rate: 10ns (DDR)
  • Read/write throughput per pin: 200 MT/s
• Asynchronous I/O performance
  • Up to asynchronous timing mode 5
  • tRC/tWC: 20ns (MIN)
• Array performance
  • Read page: 50µs (MAX)
  • Program page: 1300µs (TYP)
  • Erase block: 3ms (TYP)
• Operating Voltage Range
  • VCC: 2.7–3.6V
  • VCCQ: 1.7–1.95V, 2.7–3.6V
• Command set: ONFI NAND Flash Protocol
• Advanced Com